1. Field of the Invention
This invention relates generally to a semiconductor integrated circuit devices, and more particularly to the chip-to-lead configuration of a high-speed performance integrated circuit such as a GaAs (Gallium Arsenide) logic integrated circuit.
2. Description of the Prior Art
There has recently been significant development in the use of compound semiconductor integrated circuits that perform high-speed logic operations at frequencies in GHz. range. For example, an integrated circuit having MESFETs (Metal Semiconductor Field Effect Transistor) integrated on a GaAs substrate has been developed that achieves a high switching-speed on the order of 100 p sec. Furthermore, elements such as a HEMT (High Electron Mobility Transistor) and a HBT (Hetro-Bipolar Transistor) that perform at higher speeds have been steadily developing.
However, there have been problems in that when an integrated circuit chip which performs such a high speed operation is sealed in a package, high-speed performance is inhibited by the package. The degradation of such high-speed performance is caused at least in part by mismatched impedances of termination lead portions that receive high-speed input signals.
When high-speed input signals are fed through the signal leads into MESFETs disposed on the signal receiving sections of a GaAs logic integrated circuit, the signals are reflected at the gates of the MESFETs due to the high input impedances thereof. This reflection causes distortion of the signal waveform, and this distortion interferes with the normal logic operations. To prevent this, matching resistors are provided so as to make proper termination. For example, a GaAs logic integrated circuit chip is sealed in a conventional package and matching terminal resistors are disposed at the ends of leads which are signal input terminals.
FIG. 5 shows an equivalent circuit with such terminal resistors disposed at the end of a lead as a termination impedance. The overall arrangement includes a package 51, an integrated circuit chip 52 incorporated within the package, an inner lead 53, a MESFET 54 which is the input section of the integrated circuit chip, and a terminal resistor 55. However, in the case of a high speed integrated circuit having a switching speed on the order of 100 p sec or faster, the signal reflection problem cannot be completely solved by the use of such a matching terminal resistor disposed outside the package 51.
The configuration effectively acts like an "open stub" because the terminal resistor 55 is disposed at a point A faraway from a point B which is the gate of MESFET 54 within the package 51. Signal reflection causes ringing of input signals which results from the existence of such an open stub. To avoid this open stub, it would be necessary to incorporate the terminal resistor 55 within the package 51 in close proximity to the integrated circuit chip 52. There is contemplated an arrangement in which terminal resistors are disposed by thick-film printing within the package, or an arrangement in which chip resistors are provided. However, the inside of the package is usually not flat but stepwise, thus, it is difficult to form resistors by thick-film printing. Moreover, when a chip resistor is incorporated within the package, this requires a larger space therein. Thus such a solution is not practical.
FIG. 6 shows another so-called "feed-through" arrangement in which a terminal resistor is disposed in a manner different from that shown in FIG. 5. In FIG. 5, a first signal lead 63a from an input terminal point A of a package 61 is led through a gate terminal point B of a MESFET 64 so as to be connected through a second signal lead 63b to another terminal point C of the package 61. Namely, first and second signal leads are folded at the gate terminal point B. A terminal resistor 65 is disposed at the input terminal pint C. In this arrangement, the length of open stub becomes shorter compared to that in the FIG. 5 arrangement. However, the number of input signal leads is doubled. Therefore, as the density of integrated circuits becomes greater the number of input terminals increases and bonding pads become more dense, resulting in difficulty in connecting leads within the package. Further, in the vicinity of an input point B of folded first and second leads 63a and 63b, a branching portion 66 must be provided. The impedance branching portion 66 causes a problem in the transmission of high-speed signal waveforms.
The arrangements of both FIGS. 5 and 6 have a wire-bonding problem. When the wire-bonding is made between leads within the package and terminals on the chip of integrated circuit, the wire is usually connected in an arc. This arc-shaped bonding wire also appears to be an open stub to an integrated circuit that processes high-speed signals on the other of gigabits/sec. Thus, the length of such bonding wire cannot be ignored, and variation in length renders the characteristics of the integrated circuit non-uniform. When the density of integrated circuits becomes greater thereby causing the bonding pads to be more densely formed, the following problems also arise. First, a tool used for bonding inevitably contacts with neighboring wires such that bonding operations become impossible. Second, the size and pitch of bonding pads cannot be reduced smaller than some extent, thus the reduction in size of the integrated circuit is inevitably limited. Consequently, the length of signal leads on the chip cannot be reduced.
In order to solve the above-described problems in wire bonding, there has been provided a TAB (Tape Automated Bonding) method in which the integrated circuit chips are united on a flexible resin film. FIGS. 7a and 7b are diagrams illustrating a conventional base film for use in TAB method. FIG. 7a is a plan view of an essential portion of the base film, and FIG. 7b is a cross-sectional view thereof. In FIG. 7a, on an insulating polyamide film 71, leads 72 are formed substantially radially from a chip-mounting portion. In the chip-mounting portion, an opening is made in which an integrated circuit chip 73 is mounted. The thus mounted chip 73 has in its periphery a plurality of pads to which each end of leads 72 is respectively connected through bump electrodes. The film 71 is usually a lengthy tape on which a number of integrated circuit chip are mounted. The respective chips are separated for use by cutting off the film along the dot-and-dash line shown in FIGS. 7a and 7b. This TAB method is also called a film carrier method.
In the TAB method, the chip and leads are connected at bump electrodes, so that the inductance thereof are smaller than that in the wire-bonding method. However, in such a conventional TAB method, the signal transmission of the above-described high-speed logic integrated circuit has not been considered. Specifically, the characteristic impedance of leads on the TAB substrate is not taken into consideration, thus the reflection of signals arises due to mismatched impedance. Further, in the vicinity of the integrated circuit chip, lead pitch becomes extremely small, thus, crosstalk between leads increases. For these reasons, the high-speed signals of integrated circuit cannot be transferred with signal fidelity. This causes erroneous operations of the integrated circuit.
As described above, in the conventional chip-to-lead configuration of semiconductor integrated circuits, there have been problems such that high-speed performance cannot be fully extracted from a high-speed integrated circuit chip such as a GaAs logic integrated circuit chip.